Gate Level Simulation

Master gate-level simulation for efficient digital design

FREE

Instructor: Ramesh MaddaraLanguage: English

About the course

GLS Training Contents:

A)   GLS Basic Level: For all engineers

1.   VLSI Design Flow: Specification to Silicon Fabrication

  • This is prepared for freshers and junior engineers and may be useful to all

2.    GLS Made Easy: Introduction to GLS

  • It provides an introduction and the basic idea on the importance and need for GLS 

3.    GLS Made Easy: NRFs and X-prop basics

  • It helps to understand, Non-resettable flip-flops (NRFs). Why do they exist? And how to address them? Understanding and debugging X-propagation etc 

4.    GLS Made Easy: Non-timing GLS

  • What is non-timing GLS? Types, issues, challenges, flow/methodology, etc

5.   GLS Made Easy: Delay and Timing Concepts

  • Concepts, Gate IO delays, Timing concepts: setup, hold, clock skew, CTS, CDC, etc

B)   GLS Advanced Level: For Seniors and GLS engineers

1.   GLS Made Easy: Timing GLS, SDF File formats, and Constructs

  • Flow/Methodology, requirements, Timing Corners, strategy, etc

2.    GLS Made Easy: GLS Timing - SDF Annotation 

  • Delays annotation and checkers constraints annotation, issues, understanding standard cell library, etc

3.    GLS Made Easy: X propagation, debugging, strategies; Verdi tool

4.   GLS Made Easy: Low Power Designs and PA/PG GLS : 

  • Low Power methodology/flow, architecture, components, etc

5.   GLS Made Easy: ATE Vector Generation

Syllabus

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